1. Field of the Invention
The present invention relates to a image sensor having a plurality of lines of charge accumulation type photo-sensor arrays and also to an image sensing system utilizing such an image sensor.
2. Description of the Prior Art
In the case of image sensors or image sensing systems having a single charge accumulation type photosensor array such as a CCD (charge coupled device), it is well known to control the charge accumulation time of the photosensor array in accordance with the brightness of a target object as detected by a monitoring photosensor element arranged adjacent the photosensor array. Also in the case of image sensors or image sensing systems having a plurality of charge accumulation type photosensor arrays, proper charge accumulation time controls for the respective photosensor arrays are required in order to obtain high quality image signals without causing overtime charge accumulation in any of the photosensor arrays. However, such proper charge accumulation time controls have not been realized in prior art image sensor or image sensing system having a plurality of charge accumulation type photosensor arrays. For example, in U.S. Pat. No. 4,410,258 which discloses an image sensor employing two charge accumulation type photosensor arrays for focus detection, two monitoring photodiodes are arranged adjacent the photosensor arrays in a corresponding relation to detect the brightness of a target object, images of which are formed on the photosensor arrays. The monitoring photodiodes are connected with one another, so that the sum of their outputs is compared with a reference voltage signal to control the charge accumulation time for both of the photosensor arrays. However, since the sum of the outputs of the monitoring diodes does not always reflect the brightness of the target object whose images are formed on the photosensor arrays, correctly, it is considered that there will occur overtime charge accumulation in the photosensor arrays. In Japanese Patent Laid-Open Publication No. 59-174807, there is also disclosed an image sensing system employing a plurality of charge accumulation type photosensor arrays but there is no mention about charge accumulation time control for the respective photosensor arrays.
Another problem to be solved in image sensors or image sensing systems having a plurality of charge accumulation type photosensor arrays is how to take out the outputs of the respective photosensor arrays. If the outputs of the respective photosensor arrays are taken out parallelly with each other so as to be processed by separate processing circuits, not only the whole circuit arrangement becomes complicated but also adjustment of behaviors of the respective processing circuits becomes necessary. Therefore, it is desirable to take out the outputs of the respective photosensor arrays sequentially through a single output gate. However, in this case, the image sensors are required to hold the outputs of the photosensor arrays after termination of charge accumulation until the sequence comes to predetermined stages for taking out the respective outputs. More particularly, during a stage in which the output of one of the photosensor array is taken out, the outputs of the remaining photosensor arrays which have not been taken out should be held without being subjected to any inadvertent change. Thus, a proper measure is required to solve this problem.
Still another problem to be solved in an image sensor or image sensing system having a plurality of charge accumulation type photosensor arrays is compensation of dark current which is inherent and characteristic to the respective photosensor arrays. This problem is particularly serious when the outputs of the respective photosensor arrays are to be taken out sequentially through a single output gate so as to be processed by a single processing circuit.
Yet another problem to be solved in an image sensor or image sensing system having a plurality of charge accumulation type photosensor arrays is control of the magnitudes of the outputs of the respective photosensor arrays to be subjected to later stage processing such as A/D (analog-to-digital) conversion.
FIG. 1 shows a prior art image sensor having a single charge accumulation type photosensor array and FIG. 3 shows a driving circuit therefor. Explanation is given of the construction and operation of this prior art image sensor and the driving circuit therefor for facilitating understanding of the charge accumulation time control with use of a monitoring photosensor element.
Referring to FIG. 1, the prior art image sensor 1 includes an array of photoelectric converting elements EAn (n=1, 2, . . . , m), an array of charge accumulation elements FAn, charge shift registers CAn and CBn, a number of gates FG1, CG1, SG1, etc, and an output stage in which an output terminal T12 produces electric signals OS indicating the light intensity of an image formed on the array of the photoelectric converting elements. Provided adjacent the array of the photoelectric converting elements is a monitor photodiode MP which produces a photocurrent. A circuit MC produces from an output terminal T10 a voltage signal AGCOS indicating an integration of the photocurrent produced by the monitor photodiode MP. An output terminal T11 produces a signal DOS used as a reference voltage for signals OS and AGCOS.
Now, the description is particularly directed to the signal generated by the array of photoelectric converting elements EAn as outputted from terminal T12. When an integration clear pulse ICG (hereinafter referred to as ICG pulse) is applied at terminal T6, MOS transistors CGn provided between each charge accumulation element FAn and power source VLD turn on to initialize each charge accumulation element FAn and, at the same time, a MOS transistor MCG, connected between the power source VLD and a floating gate MGF for monitor photodiode MP, turns on to clear the output of the monitor photodiode MP. In this operation, all the photoelectric converting elements EAn are once charged up to a level approximately equal to the voltage of the power source.
Thereafter, when the ICG pulse disappears, the discharge starts at a speed relative to the intensity of the light impinging on each photoelectric converting element. Since such a discharge can be regarded as a negative charge, the term "charge" used herein does not only mean the charge in the positive direction, but also in the negative direction. Then, the charge which is in radiation to the intensity of light impinging on each photoelectric converting element EAn and as generated from each photoelectric converting element EAn is transferred through the respective floating gate FGn to the corresponding charge accumulation element FAn. The charge produced by the monitor photodiode MP is transmitted through the floating gate MFG to a charge accumulation capacitor, thereby producing from terminal T10 the signal AGCOS representing, at real time, the condition of the accumulated charge. When the level of the signal AGCOS drops to a predetermined level, indicating that each photoelectric converting element EAn has produced an appropriate amount of charge for processing the signal in the later stage, an SH pulse is applied to turn the gate SGn on, thereby transmitting the charges accumulated in the charge accumulation elements FAn parallelly to the corresponding charge shift registers CAn. Thus, the charge integration is completed.
Each shift gate SGn defines a potential well during the "HIGH" period of the transfer clock .PHI.1, which is provided for driving the charge shift registers CAn. Since shift gates SGn are connected to the corresponding charge shift registers CAn, it is necessary to synchronize the generation of the shift pulse SH with the phase of the transfer clock .PHI.1 such that shift pulse SH of a HIGH level is generated after the transfer clock .PHI.1 is made HIGH and transfer clock .PHI.2 is made LOW to define the potential well in connection to the shift registers CAn. Thus, in response to the generation of the shift pulse SH, the MOS transistors SGn connected between the charge accumulation elements FAn and shift registers CAn turn on to inject the charges accumulated during the integration period in the potential well.
Thereafter, in response to the HIGH level of the clock pulse .PHI.1, the charges stored in shift registers CAn are simultaneously transferred to adjacent shift registers CBn located, when viewed in FIG. 1, on the right hand side of the shift register CAn. Then, in response to the HIGH level of the clock pulse .PHI.2, the charges stored in shift registers CBn are simultaneously transferred to adjacent shift registers CAn-1. Thus, in response to the trailing edge of each clock pulse .PHI.1, the charges are outputted sequentially from the shift register CB0 located at the most right-hand side of the array. Thus, the first charge that will be outputted in synchronization with the trailing edge of the clock pulse .PHI.1 from the shift register CB0 will be the charge generated by the photoelectric converting element EA1. The charges outputted from the shift register CB0 are converted by a buffer circuit Vs to voltage signals, and are outputted from terminal T12 as voltage signals OS.
The circuit shown in FIG. 3 is disclosed, for example, in U.S. patent application Ser. No. 763,338 assigned to the same assignee as the present application. In FIG. 3, a reference number 1 designates the image sensor; 10 designates transfer clock pulse generator; 20 designates a digital signal generator for generating, in response to the signal obtained from the image sensor, digital signals which will be used as a base for detecting the focusing condition of the camera's objective lens; and 30 is a microcomputer which determines, using the digital signal from the circuit 20, the focusing condition of the camera's objective lens and also controls the operation of various circuits.
A reference number 40 is a brightness detecting circuit, a detail of which is shown in FIG. 4, for detecting the brightness of the object based on the output of the brightness monitoring circuit provided in the image sensor 1 to control the amplification of the amplifier OP provided in the circuit 20 and also for controlling the charge accumulation time (photocurrent integration time) in the image sensor 1; AN1 and AN2 are AND gates which define a gate means together with an OR gate OR1; DF1 is a D flip-flop which generates a reset pulse that resets flip-flops FF0, and flip-flops FF1-FF6 (described later); DF2 is a D flip-flop for generating a shift pulse SH for shifting charges accumulated in the charge accumulation elements FAn to charge shift registers CAn; CL1 is a clock pulse generator for generating standard clock pulses; and FF0 is an R-S flip-flop.
As shown in FIG. 3, the shift clock pulse generator 10 for generating transfer clock pulses .PHI.1 and .PHI.2 includes flip-flops FF1-FF6 for dividing the clock pulses. The first flip-flop FF1 receives to its T terminal the clock pulses (one cycle period=2 microseconds) from the clock pulse generator CL1. The Q terminals of flip-flop FF3, FF4, FF5 and FF6 are connected inputs of OR gate OR2 which is in turn connected to one input of AND gate AN4. The other input of the AND gate AN4 is connected through an inverter IN1 to a terminal T22 of microcomputer 30. When terminal T22 produces a signal of logic "0", AND gate AN4 is enabled to permit the signal "1" from OR gate OR2 to pass therethrough. An AND gate AN5 has its one input connected to a clock pulse generator CL2 and the other input thereof connected to terminal T22. Thus, when terminal T22 produces a signal of logic "1", AND gate AN5 is enabled to transmit the clock pulses from generator CL2 to pass therethrough. It is to be noted that the clock pulses as generated from generator CL2 has a frequency which is several tens times higher than the frequency of the pulse as produced from the Q terminal of flip-flop FF6. OR gate OR3 produces a signal of logic "1" when either AND gate AN4 or AN5 produces a signal of logic "1" and applies it to shift registers CBn as a clock pulse .PHI.2. An inverter IN2 connected to OR gate OR3 produces a clock pulse, having a phase opposite to the clock pulse produced from OR gate OR3, and applies it to shift registers CAn as a clock pulse .PHI.1 and also to an image signal producing circuit VS. It is to be noted that the signal of logic "1" as produced from terminal T22 of microcomputer 30 is for effecting the initialize of the image sensor.
In FIG. 4, examples of the brightness detecting circuit 40 and the digital signal generator 20 are shown. In the drawing, reference characters T10, T11 and T12 designate terminals for receiving signals AGCOS, DOS and OS, respectively. Applied to terminal T13 is the shift pulse SH from D flip-flop DF2, and to terminals T15 and T16 are sampling start pulse and sampling stop pulse from microcomputer 30 through data bus DB1 in a manner which will be described later. Terminal T14 is connected to one input of AND gate AN2 shown in FIG. 3.
Brightness detecting circuit 40 has comparators AC1, AC2, AC3 and AC4 for detecting the rate of decrease of the voltage signal AGCOS from the brightness monitor circuit MC after the disappearance of the integration clear pulse ICG. The inverting inputs of the comparators AC1-AC4 are connected through a buffer B1 to terminal T10. The non-inverting inputs of the comparators AC1-AC4 are connected, respectively, to a junction J4 between a resistor R1 and a constant current source I1, a junction J5 between a resistor R2 and a constant current source I2, a junction J6 between a resistor R3 and a constant current source I3, and a junction J7 between a resistor R4 and a constant current source I4. Resistors R1, R2, R3 and R4 are connected through buffer B2 to terminal T11. By the above arrangement, a voltage equal to the reference voltage DOS from the reference voltage generator RS subtracted by a voltage drop across resistor R1 will be produced at junction J4. Similarly, a voltage equal to the reference voltage DOS subtracted by a voltage drop across resistor R2 will be produced at junction J5; a voltage equal to the reference voltage DOS subtracted by a voltage drop across resistor R3 will be produced at junction J6; and a voltage equal to the reference voltage DOS subtracted by a voltage drop across resistor R4 will be produced at junction J7. By selecting appropriate resistances for registers R1, R2, R3 and R4 and appropriate currents from constant current sources I1, I2, I3 and I4, the gradual decrease of the voltage AGCOS will result in the sequential state change, from "0" producing state to "1" producing state, of comparators AC1, AC2, AC3 and AC4. The outputs of comparators AC1, AC2 and AC3 are connected to D terminals of D flip-flops DF3, DF4 and DF5 having their CP terminals connected to the Q terminal of D flip-flop DF2 for receiving the shift pulse. Upon receipt of the shift pulse, D flip-flops DF3, DF4 and DF5 shifts the signals applied to the D terminals from comparators AC1, AC2 and AC3 to the Q terminals and, at the same time, produces opposite signals from the Q terminals. AND gate AN6 has one input connected to the Q terminal of D flip-flops DF3 and the other input connected to the Q terminal of D flip-flop D4. AND gate AN7 has one input connected to the Q terminal of D flip-flop DF4 and the other input connected to the Q terminal of D flip-flop DF5. The outputs b and c from AND gates AN6 and AN7, the Q output from a D flip-flop DF3, the Q output d from flip-flop DF5 and the output e from comparator AC4 are the outputs from the brightness detecting circuit 40 which carry information on the brightness level as detected by the monitor photodiode MP.
The other circuits shown in FIG. 4 define circuit 20 shown in FIG. 3. A reference number 22 designates a subtractor for producing a difference signal V1 which represents a difference between the voltage signal VOS as applied through terminal T12 and buffer B3 from the image signal producer VS and the voltage signal DOS as applied through terminal T11 and buffer B2 from the reference voltage generator RS. A reference number 24 is a peak detector for detecting and holding the peak value V2 (peak value in the negative direction) of the accumulated charges obtained from the photoelectric converting elements EAn covered completely with an aluminum mask (that is, not including the elements under the opposite ends of the aluminum mask). The signal V2 will be used for compensation for the dark output signal. Terminals T15 and T16 are provided for receiving the sampling start and sampling stop pulses from microcomputer 30 through data bus DB1 so as to determine the sampling period in the peak detector 24.
A reference number 26 designates a gain controllable differential amplifier for amplifying the difference between signals V1 and V2 as obtained from circuits 22 and 24. The gain (mu-factor) of the operational amplifier OP is determined by the signals a, b, c and d obtained from the brightness detector 40. The operational amplifier OP has two inputs f and g which are connected through input resistors R5 and R6 to circuits 22 and 24, respectively. Resistors R7-R14 are provided for selectively setting the gain of operational amplifier OP. The resistance of the resistors are so selected that resistors R5, R6, R7, R8, R11 and R12 have resistance r, resistors R9 and R13 have resistance 2r and resistors R10 and R14 have resistance 4r. Analog switches AS1-AS8 are provided in which analog switches AS1-AS4 are coupled to registers R10, R9, R8 and R7, respectively, for selectively determining the feedback resistance value of the operational amplifier OP in accordance with the signals obtained from the outputs a, b, c and d, and in which analog switches AS5-AS8 are coupled to resistors R14, R13, R12 and R11, respectively, for selectively determining the bias resistance value of the operational amplifier OP. Accordingly, the output voltage Vout of the operational amplifier OP can be expressed as follows. EQU Vout=E+(V2-V1).times.A
wherein A is the gain A of the operational amplifier OP and E is a constant voltage. The output voltage Vout is applied to an A/D (analog-to-digital) converter ADC. The constant voltage E is set at an appropriate level in consideration of the dynamic range of the A/D converter ADC. The signals produced from the A/D converter ADC are applied through data bus DB1 to microcomputer 30 for being used to detect the focusing condition of the objective lens. In this manner, the amplifier circuit 26 changes its gain in accordance with the output signal from the brightness detecting circuit 40 and produces voltage signals which are appropriate for being processed in the A/D converter ADC and, therefore, it is possible to control the focusing condition with a wide range of brightness change.
Referring again to FIG. 3, microcomputer 30 has a terminal T17 from which the integration clear pulse ICG is produced. Also, from terminal T19 of the microcomputer 30, a signal of logic "1" is produced for permitting the generation of the shift pulse, and a signal of logic "0" is produced for prohibiting the generation of the shift pulse during the transfer of the accumulated charges from the photoelectric converting elements EAn to charge shift registers CAn. From terminal T18 of the microcomputer 30, a signal of logic "1" is produced when no specific pulse is generated from the terminal T14 of the brightness detector 40 during a predetermined time from a time t0 at which the integration clear pulse ICG disappeared. The integration clear pulse as produced from terminal T17 is applied through terminal T6 to the integration clear gate ICG of the image sensor 1, and is also applied to flip-flop FF0 which thereupon produces a signal of logic "1" from its Q terminal thereby enabling AND gate AN1. Under this condition, if terminal T19 also produces a signal of logic "1", AND gate AN2 is also enabled. When the object is brighter than a certain level, terminal T14 of brightness detecting circuit 40 produces a signal of logic "1" along lines e at moment t2 which is before counting a predetermined period (100 ms) from time t0 when the integration clear pulse disappeared. When the object is less brighter than the certain level, terminal T18 of the microcomputer 30 produces a signal of logic "1" at time t3 that is when the predetermined period (100 ms) has been counted from time t0. Accordingly, when the object is bright, AND gate AN2 produces a signal of logic "1" at time t2, and when the object is dark, AND gate AN1 produces a signal of logic "1" at time t3. OR gate OR1 transmits the signal of logic "1" either from AND gate AN1 or AN2 and applies it to D input of D flip-flop DF1. Clock terminal CK of the D flip-flop DF1 receives standard clock pulses (one cycle period is 2 microseconds) from clock pulse generator CL1, so that D flip-flop DF1 produces from its Q terminal a signal of logic "1" in response to the trailing edge of the standard clock pulse applied immediately after the input of the signal of logic "1" to its D terminal, thereby resetting flip-flop FF0. Thus, AND gates AN1 and AN2 are disabled and, at the same time, flip-flops FF1-FF6 provided in transfer clock pulse generators 10 are reset, thereby producing signals of logic "0" from Q terminals Q1-Q6 of flip-flops FF1-FF6. Then, after the AND gates AN1 and AN2 are disabled, the Q terminal of flip-flop DF1 produces a signal of "0" in response to the trailing edge of the next standard clock pulse. As a result, flip-flop DF1 produces from its Q terminal a positive going pulse having a pulse duration of 2 microseconds. This pulse is used as a reset pulse.
Similarly, D flip-flop DF2 produces a signal of logic "1" from its Q terminal in response to the trailing edge of a standard clock pulse produced from clock generator CL1 immediately after the generation of the signal of logic "1" from the Q terminal of D flip-flop DF1, and thereafter, it produces a signal of logic "0" from its Q terminal in response to the trailing edge of a standard clock pulse immediately after the generation of the signal of logic "0" from the Q terminal of D flip-flop DF1. Therefore, from the Q terminal of D flip-flop DF2, a positive going pulse having a pulse duration of 2 microseconds and synchronized with the trailing edge of the reset pulse is produced. This pulse is used as a shift pulse SH. The shift pulse is applied to terminal T21 of the microcomputer 30 and, at the same time, through terminal T7 to shift gates SGn of image sensor 1.
The operation of the above described circuit will now be described with reference to FIG. 2 showing a time chart of shift pulse generation under the condition aiming a bright object. By the ICG pulse, a capacitor provided in circuit MC is fully charged by power source VLD, and a voltage signal AGCOS which is in relation to VLD is produced from terminal T10. When the ICG pulse disappears, charge accumulation takes place at the rate relative to the brightness of the object to gradually decrease the voltage signal AGCOS. Then, when the voltage signal AGCOS is decreased to a predetermined level V=R4.times.I4, at time t2, the output T14 of comparator AC4 inverts from "0" to "1". It is preferable to end the charge accumulation at the time when the output T14 is inverted, but according to the prior art circuit of FIG. 3, the charge accumulation ends with a delay being 4 microseconds at minimum and 6 microseconds at maximum, as explained below. In response to the inversion of the output T14, flip-flop DF1 changes its state, with a maximum delay of 2 microseconds, and after another delay of 2 microseconds, flop-flop DF2 produces a shift pulse SH. By the trailing edge of the shift pulse SH, charges are transferred from charge accumulation elements FAn to registers CAn, thereby actually ending the charge accumulation. Since the shift pulse SH is also formed by using the standard clock pulse having pulse duration of 2 microseconds, the charge accumulation (light integration) in the charge accumulation elements FAn always accompanies overtime charge accumulation ranging from 4 microseconds to 6 microseconds. In other words, the charge accumulation actually ends after a delay of 4 microseconds at the minimum and 6 microseconds at the maximum from the inversion of the signal at terminal T14 from "0" to "1". This will result in undesirable increase of the average output of the photoelectric converting elements and, therefore, the signals to be processed in the later stage will be saturated if the target object has a high brightness. Accordingly, the overtime charge accumulation due to the delay in the ending of charge accumulation from the inversion of the signal at terminal T14 itself is a drawback of the prior art driving circuit of FIG. 3.